284044-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

  PIC18F2455/2550/4455/4550 Data Sheet 28/40/44-Pin, High-Performance,

Enhanced Flash, USB Microcontrollers

with nanoWatt Technology

  • • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

    intended manner and under normal conditions.
  • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
  • Microchip is willing to work with the customer who is concerned about the integrity of their code.
  • • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

    mean that we are guaranteeing the product as “unbreakable.”

    Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

    products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

    allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

  Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR

  IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,

  INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

  Trademarks The Microchip name and logo, the Microchip logo, dsPIC, K EE L OQ , K EE L OQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

  FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

  Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC

  32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

  Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet.

  PIC18F2455/2550/4455/4550 Universal Serial Bus Features:

  • High-Current Sink/Source: 25 mA/25 mA
  • Three External Interrupts • Four Timer modules (Timer0 to Timer3)
  • Up to 2 Capture/Compare/PWM (CCP) modules:
  • USB V2.0 Compliant • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
  • Supports Control, Interrupt, Isochronous and Bulk Transfers • Supports up to 32 Endpoints (16 bidirectional)
  • 1 Kbyte Dual Access RAM for USB
  • On-Chip USB Transceiver with On-Chip Voltage Regulator • Interface for Off-Chip USB Transceiver • Streaming Parallel Port (SPP) for USB streaming transfers (40/44-pin devices only)
    • Capture is 16-bit, max. resolution 5.2 ns (T CY /16)
    • Compare is 16-bit, max. resolution 83.3 ns (T CY )
    • PWM output: PWM resolution is 1 to 10-bit

  • Enhanced Capture/Compare/PWM (ECCP) module:
    • Multiple output modes
    • Selectable polarity
    • Programmable dead time
    • Auto-shutdown and auto-restart

  Power-Managed Modes:

  • Enhanced USART module:
  • Run: CPU on, Peripherals on
  • Idle: CPU off, Peripherals on
  • Sleep: CPU off, Peripherals off
  • Idle mode Currents Down to 5.8 μA Typical • Sleep mode Currents Down to 0.1 μA Typical • Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
  • Watchdog Timer: 2.1 μA Typical • Two-Speed Oscillator Start-up
    • LIN bus support

  • Master Synchronous Serial Port (MSSP) module

  • 10-Bit, Up to 13-Channel Analog-to-Digital Converter (A/D) module with Programmable Acquisition Time • Dual Analog Comparators with Input Multiplexing

  Flexible Oscillator Structure:

  Peripheral Highlights:

  Supporting 3-Wire SPI (all 4 modes) and I

  2 C™

  Master and Slave modes

  Special Microcontroller Features:

  • C Compiler Optimized Architecture with Optional Extended Instruction Set • 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical • 1,000,000 Erase/Write Cycle Data EEPROM
    • 8 user-selectable frequencies, from 31 kHz to 8 MHz
    • User-tunable to compensate for frequency drift

  • Flash/Data EEPROM Retention: > 40 Years • Self-Programmable under Software Control • Priority Levels for Interrupts
  • Secondary Oscillator using Timer1 @ 32 kHz

  • Four Crystal modes, including High-Precision PLL for USB
  • Two External Clock modes, Up to 48 MHz
  • Internal Oscillator Block:

  Memory Typical

  

28/40/44-Pin, High-Performance, Enhanced Flash,

USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550

  • /CV

  RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP

  REF

  REF

  /RE3 RA0/AN0 RA1/AN1 RA2/AN2/V

  V DD MCLR/V PP

  RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA

  (1) /VPO RB2/AN8/INT2/VMO

  V SS RC7/RX/DT/SDO RC6/TX/CK RC5/D+/VP

  1

  V DD

  RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA

  (1) /VPO RB2/AN8/INT2/VMO

  V USB RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2

  (1) /UOE RC2/CCP1

  V SS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI

  REF

  3

  2

  38

  32

455

550

  33

  34

  35

  36

  37

  39

  REF

  40

  9

  8

  7

  6

  5

  4

  REF

  REF

  21 MCLR/V PP /RE3 RA0/AN0 RA1/AN1 RA2/AN2/V

  11

  22

  6

  5

  4

  3

  2

  10

  7

  50

  25

  

55

28-Pin PDIP, SOIC PIC18 F

  

24

  

PIC18

F

  Pin Diagrams 40-Pin PDIP

  8

  1

  9

  20

  28

  27

  26

  12

  24

  23

  25

RA3/AN3/V

  • RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT

  19

  18

  17

RC1/T1OSI/CCP2

  16

  15

  14

  13

RC4/D-/VM

  • /CV

RA3/AN3/V

  • RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT RE0/AN5/CK1SPP RE1/AN6/CK2SPP

RB3/AN9/CCP2

PIC18F2455/2550/4455/4550

  2 (1 )

  (1) /VPO RD7/SPP7/P1D

  26

  27

  28

  

36

  34

  35

NC/ICRST

  9

  37 RA3 /AN3 /V RE F

OSC1/CLKI

  3 NC/

  4

  5

  V DD RB0/AN12/INT0/FLT0/SDI/SDA RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO

  24

  RC6 /T X /CK

  1 O SI/CCP

  RC1 /T

  V US B

RC2

/CCP1

/P1

A

  RD1 /SPP1 RD0 /SPP0

  RD3 /SPP3 RD2 /SPP2

  RC5 /D+/VP RC4 /D- /V M

  ICPOR T S (2 )

  V SS

  (2) /ICV

  PP (2)

  RC0/T1OSO/T13CKI OSC2/CLKO/RA6

  V SS

  V DD RE2/AN7/OESPP RE1/AN6/CK2SPP RE0/AN5/CK1SPP RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT/RCV

  RC7/RX/DT/SDO RD4/SPP4 RD5/SPP5/P1B RD6/SPP6/P1C

  25

  23

  /U O E NC/

  42

  3

  2

  33

  38

  8

  7

  44

  43

  41

  1

  40

  39

  10

  Pin Diagrams (Continued) PIC18F4455 44-Pin TQFP 44-Pin QFN PIC18F4550

  29

  30

  31

  32

  6

RB3/AN9/CCP2

  21

  

20

  19

  18

  22

  12

  13

  14

  11

  16

  17

  15

  • RA2 /AN

  G D (2 )

  • /C
    • /VP RC4 /D

  • /

  36

  34

  35

  37 RC6 /T X/CK RC5

  /D

  VM RD3 /SPP3 RD2

  /SPP2 RD1 /SPP1 RD0

  /SPP0

  V US B RC2 /C CP

  1 /P1 A RC1

  /T

  1 O S I/CCP2 (1 )

  /UOE RC0 /T

  1 O SO/T

  1

  3 CKI OSC2/CLKO/RA6 OSC1/CLKI

  V SS RC7/RX/DT/SDO RD4/SPP4 RD5/SPP5/P1B

  V SS

  MC LR /V PP /RE

  V RE F

RA1

/AN1

RA0 /AN0

  2 /V RE F

  33

  32

  31

  ICCK (2 ) /ICP

  I0 /C SSPP NC/ICDT

  1 /K B

  /AN1

  5 /KBI 1 /P G M RB4

  I2 /P GC RB

  6/ K B

  I3 /P GD RB

  RB 7/ K B

  G C (2 )

  2

  30

  3

  1

  38

  44

  43

  42

  41

  40

  39

  (2 ) /ICP

  PIC18F2455/2550/4455/4550 Table of Contents

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

......................................................................................................... 421

Appendix F:

PIC18F2455/2550/4455/4550

  

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

  Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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PIC18F2455/2550/4455/4550

  NOTES:

PIC18F2455/2550/4455/4550

  1.0 DEVICE OVERVIEW

  This document contains device-specific information for the following devices: This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. In addition to these features, the PIC18F2455/2550/4455/4550 family introduces design enhancements that make these microcontrollers a log- ical choice for many high-performance, power sensitive applications.

  1.1.3 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

  All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include:

  • PIC18F2455 • PIC18LF2455
  • PIC18F2550 • PIC18LF2550
  • PIC18F4455 • PIC18LF4455
  • PIC18F4550 • PIC18LF4550<
  • Four Crystal modes using crystals or ceramic resonators.
  • Four External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).
  • An internal oscillator block which provides an

  1.1 New Core Features

  8 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and V DD ), as well as a range of 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O.

  • A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and External Oscillator modes, which allows a wide range of clock speeds from 4 MHz to 48 MHz.
  • Asynchronous dual clock operation, allowing the

  1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F2455/2550/4455/4550 family incorporate a range of features that can signifi- cantly reduce power consumption during operation. Key items include:

  USB module to run from a high-frequency oscillator while the rest of the microcontroller is clocked from an internal low-power oscillator. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:

  • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.
  • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4%, of normal operation requirements.
  • On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.
  • >Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.
  • Two-Speed Start-up: This option allows the
  • PIC18F2455/2550/4455/4550

    1.2 Other Special Features

      1.3 Details on Individual Family Members

    • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.
    • Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine, located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.
    • Extended Instruction Set: The PIC18F2455/2550/4455/4550 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Literal Offset Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as C.
    • Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown for disabling PWM outputs on interrupt or other select conditions, and auto-restart to reactivate outputs once the condition has cleared.
    • Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. The TX/CK and RX/DT signals can be inverted, eliminating the need for inverting buffers. Other enhancements include Automatic Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without

      Devices in the PIC18F2455/2550/4455/4550 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown

      The devices are differentiated from each other in six ways:

      1. Flash program memory (24 Kbytes for PIC18FX455 devices, 32 Kbytes for PIC18FX550 devices).

      2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices).

      3. I/O ports (3 bidirectional ports and 1 input only port on 28-pin devices, 5 bidirectional ports on 40/44-pin devices).

      4. CCP and Enhanced CCP implementation (28-pin devices have two standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module).

      5. Streaming Parallel Port (present only on 40/44-pin devices). All other features for devices in this family are identical. These are summarized in The pinouts for all devices are listed in Like all Microchip PIC18 devices, members of the PIC18F2455/2550/4455/4550 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2550), accommodate an operating V

      DD range of 4.2V to 5.5V.

      Low-voltage parts, designated by “LF” (such as PIC18LF2550), function over an extended V DD range of 2.0V to 5.5V.

    PIC18F2455/2550/4455/4550

      TABLE 1-1: DEVICE FEATURES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

      Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 24576 32768 24576 32768 Program Memory (Instructions) 12288 16384 12288 16384 Data Memory (Bytes) 2048 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources

      19

      19

      20

      20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers

      4

      4

      4

      4 Capture/Compare/PWM Modules

      2

      2

      1

      1 Enhanced Capture/

      1

      1 Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP,

      Enhanced USART Enhanced USART Enhanced USART Enhanced USART Universal Serial Bus (USB)

      1

      1

      1

      1 Module Streaming Parallel Port (SPP) No No Yes Yes 10-Bit Analog-to-Digital Module

      10 Input Channels

      10 Input Channels

      13 Input Channels

      13 Input Channels Comparators

      2

      2

      2

      2 Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction,

      Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow

      (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional),

      WDT WDT WDT WDT Programmable Low-Voltage Yes Yes Yes Yes Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set

      75 Instructions;

      75 Instructions;

      75 Instructions;

      75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set enabled enabled enabled enabled

      Packages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN

      PIC18F2455/2550/4455/4550 FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM Data Bus&lt;8&gt;

      Table Pointer&lt;21&gt; PORTA RA0/AN0

      Data Latch

      8

      8 RA1/AN1 inc/dec logic REF REF

      RA2/AN2/V -/CV Data Memory

      RA3/AN3/V (2 Kbytes) PCLATU PCLATH

    • REF

      21 RA4/T0CKI/C1OUT/RCV Address Latch

      20 RA5/AN4/SS/HLVDIN/C2OUT PCU PCH PCL OSC2/CLKO/RA6 Program Counter

      12 Data Address&lt;12&gt;

      31 Level Stack

      4

      12

      4 Address Latch Access BSR FSR0

      Program Memory STKPTR Bank (24/32 Kbytes) FSR1

      FSR2

      12 Data Latch PORTB RB0/AN12/INT0/FLT0/SDI/SDA inc/dec RB1/AN10/INT1/SCK/SCL

      8 logic RB2/AN8/INT2/VMO Table Latch

      (3) RB3/AN9/CCP2 /VPO RB4/AN11/KBI0

      Address RB5/KBI1/PGM ROM Latch Decode

      Instruction Bus &lt;16&gt; RB6/KBI2/PGC RB7/KBI3/PGD

      IR

      8 Instruction State Machine Decode &amp; Control Signals

      Control PRODH PRODL PORTC 8 x 8 Multiply

      RC0/T1OSO/T13CKI

      3 (3)

      8 RC1/T1OSI/CCP2 /UOE (2)

      Internal OSC1 Power-up RC2/CCP1 BITOP W

      Oscillator Timer RC4/D-/VM

      8

      8 Block

      8 (2)

      RC5/D+/VP Oscillator OSC2

      RC6/TX/CK Start-up Timer

      INTRC

      8

      8 RC7/RX/DT/SDO Oscillator Power-on T1OSI

      Reset

      8 MHz ALU&lt;8&gt; Watchdog Oscillator

      T1OSO Timer

      8 Brown-out (1)

      Single-Supply MCLR Reset Programming

      Fail-Safe In-Circuit DD SS

      V ,

      V Clock Monitor Debugger PORTE Band Gap

      USB Voltage USB

      V

      PIC18F2455/2550/4455/4550 FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM Data Bus&lt;8&gt;

      PORTA Table Pointer&lt;21&gt; RA0/AN0 Data Latch RA1/AN1

      8

      8 inc/dec logic REF REF

      RA2/AN2/V -/CV Data Memory

      RA3/AN3/V (2 Kbytes) PCLATU PCLATH

    • REF

      RA4/T0CKI/C1OUT/RCV

      21 RA5/AN4/SS/HLVDIN/C2OUT Address Latch

      20 OSC2/CLKO/RA6 PCU PCH PCL Program Counter

      12 Data Address&lt;12&gt; PORTB

      31 Level Stack RB0/AN12/INT0/FLT0/SDI/SDA

      4

      12

      4 Address Latch RB1/AN10/INT1/SCK/SCL BSR Access

      FSR0 RB2/AN8/INT2/VMO Program Memory STKPTR Bank

      (4) (24/32 Kbytes) FSR1 RB3/AN9/CCP2 /VPO

      FSR2 RB4/AN11/KBI0/CSSPP

      12 Data Latch RB5/KBI1/PGM RB6/KBI2/PGC inc/dec RB7/KBI3/PGD

      8 logic Table Latch PORTC

      Address ROM Latch Decode

      Instruction Bus &lt;16&gt; RC0/T1OSO/T13CKI

      (4) RC1/T1OSI/CCP2 /UOE RC2/CCP1/P1A

      IR RC4/D-/VM RC5/D+/VP

      8 RC6/TX/CK RC7/RX/DT/SDO Instruction State Machine

      Decode &amp; Control Signals Control PRODH PRODL

      PORTD 8 x 8 Multiply

      3 DD SS V , V

      8 Internal Power-up RD0/SPP0:RD4/SPP4

      (2) Oscillator

    BITOP W

      OSC1 Timer Block

      RD5/SPP5/P1B

      8

      8

      8 (2)

      RD6/SPP6/P1C OSC2 Oscillator

      INTRC RD7/SPP7/P1D Start-up Timer

      Oscillator T1OSI

      8

      8 Power-on

      8 MHz T1OSO Reset ALU&lt;8&gt;

      Oscillator Watchdog

      8 (3)

      Timer

      ICPGC Single-Supply Programming Brown-out

      (3)

      ICPGD PORTE Reset

      In-Circuit RE0/AN5/CK1SPP

      (3)

      ICPORTS Debugger Fail-Safe RE1/AN6/CK2SPP Clock Monitor Band Gap

      (3) RE2/AN7/OESPP

      ICRST (1)

      Reference PP MCLR/V /RE3

    PIC18F2455/2550/4455/4550

      TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP, SOIC

      MCLR/V /RE3 1 Master Clear (input) or programming voltage (input).

      PP

      MCLR

      I ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

      V P Programming voltage input.

      PP

      RE3 I ST Digital input. OSC1/CLKI 9 Oscillator crystal or external clock input.

      OSC1 I Analog Oscillator crystal input or external clock source input. CLKI

      I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6 10 Oscillator crystal or clock output.

      OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin.

      Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

      ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

    2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

    PIC18F2455/2550/4455/4550

      7 I/O

      I O

      I ST ST —

      TTL Digital I/O.

      Timer0 external clock input. Comparator 1 output. External USB transceiver RCV input.

      RA5/AN4/SS/ HLVDIN/C2OUT

      RA5 AN4 SS HLVDIN C2OUT

      I I

      RA4/T0CKI/C1OUT/RCV RA4 T0CKI C1OUT RCV

      I O TTL Analog

      TTL Analog

      — Digital I/O.

      Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

      RA6 — — — See the OSC2/CLKO/RA6 pin.

      TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP, SOIC Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

      ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

      6 I/O

      PORTA is a bidirectional I/O port. RA0/AN0

      RA0 AN0

      Analog input 1. RA2/AN2/V REF -/CV REF

      2 I/O

      I TTL Analog Digital I/O.

      Analog input 0. RA1/AN1

      RA1 AN1

      3 I/O

      I TTL Analog Digital I/O.

      RA2 AN2

      I I TTL Analog Analog Digital I/O.

      V REF - CV REF

      4 I/O

      I I O TTL Analog Analog Analog Digital I/O.

      Analog input 2. A/D reference voltage (low) input. Analog comparator reference output.

      RA3/AN3/V REF + RA3 AN3

      V REF +

      5 I/O

      Analog input 3. A/D reference voltage (high) input.

    PIC18F2455/2550/4455/4550

      PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/FLT0/ SDI/SDA

      RB0 AN12

      INT0 FLT0 SDI SDA

      21 I/O

      I I

      I I I/O

      TTL Analog

      ST ST ST ST Digital I/O.

      Analog input 12. External interrupt 0. PWM Fault input (CCP1 module). SPI data in.

      TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP, SOIC

    2 C™ data I/O.

      22 I/O

      I I/O O TTL

      I

      RB1/AN10/INT1/SCK/ SCL RB1 AN10

      Interrupt-on-change pin.

      I TTL TTL Digital I/O.

      26 I/O

      RB5/KBI1/PGM RB5 KBI1

      Analog input 11. Interrupt-on-change pin.

      TTL Digital I/O.

      I I TTL Analog

      25 I/O

      RB4 AN11 KBI0

      Analog input 9. Capture 2 input/Compare 2 output/PWM2 output. External USB transceiver VPO output. RB4/AN11/KBI0

      — Digital I/O.

      Analog ST

      24 I/O

      I I I/O I/O

      VPO

      (1)

      RB3 AN9 CCP2

      Analog input 8. External interrupt 2. External USB transceiver VMO output. RB3/AN9/CCP2/VPO

      ST — Digital I/O.

      INT1 SCK SCL

      23 I/O

      VMO

      INT2

      RB2/AN8/INT2/VMO RB2 AN8

      2 C mode.

      Analog input 10. External interrupt 1. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

      ST ST ST Digital I/O.

      TTL Analog

      I I O TTL Analog

    PIC18F2455/2550/4455/4550

      EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT).

      16 I I/O

      O TTL —

      TTL Digital input.

      USB differential plus line (input/output). External USB transceiver VP input.

      RC6/TX/CK RC6 TX CK

      17 I/O O

      I/O ST

      — ST Digital I/O.

      RC7/RX/DT/SDO RC7 RX DT SDO

      RC5/D+/VP RC5 D+

      18 I/O

      I I/O O ST ST ST

      — Digital I/O.

      EUSART asynchronous receive. EUSART synchronous data (see TX/CK). SPI data out.

      RE3 — — — See MCLR/V

      PP /RE3 pin.

      V USB

      14 P — Internal USB 3.3V voltage regulator output, positive supply for internal USB transceiver.

      TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP, SOIC

      VP

      PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI

      RC0 T1OSO T13CKI

      — Digital I/O.

      11 I/O O

      I ST —

      ST Digital I/O.

      Timer1 oscillator output. Timer1/Timer3 external clock input.

      RC1/T1OSI/CCP2/UOE RC1 T1OSI CCP2

      (2)

      UOE

      12 I/O

      I I/O O ST CMOS ST

      Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. External USB transceiver OE output.

      TTL Digital input.

      RC2/CCP1 RC2 CCP1

      13 I/O I/O

      ST ST Digital I/O.

      Capture 1 input/Compare 1 output/PWM1 output. RC4/D-/VM

      RC4

      D-

      VM

      15 I I/O

      I TTL —

      USB differential minus line (input/output). External USB transceiver VM input.

    PIC18F2455/2550/4455/4550

      TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP

      MCLR/V /RE3

      1

      18 18 Master Clear (input) or programming voltage (input).

      PP

      MCLR

      I ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

      V P Programming voltage input.

      PP

      RE3 I ST Digital input. OSC1/CLKI

      13

      32 30 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI

      I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6

      14

      33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

      CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin.

      Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

      ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

      2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

    3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

    Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

    PIC18F2455/2550/4455/4550

      TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type

    Buffer

    Type

      PORTA is a bidirectional I/O port. RA0/AN0

      RA0 AN0

      2

      19

      19 I/O

      I TTL Analog Digital I/O.

      Analog input 0. RA1/AN1

      RA1 AN1

      3

      20

      20 I/O

      I TTL Analog Digital I/O.

      Analog input 1. RA2/AN2/V

      Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

    • / CV

      RA2 AN2

    • CV
      • RA3 AN3
      • 5

      Timer0 external clock input. Comparator 1 output. External USB transceiver RCV input.

      RA5/AN4/SS/ HLVDIN/C2OUT

      RA5 AN4 SS HLVDIN C2OUT

      7

      24

      24 I/O

      I I

      I O TTL Analog

      I ST ST —

      TTL Analog

      — Digital I/O.

      Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output.

      RA6 — — — — — See the OSC2/CLKO/RA6 pin.

      REF

      REF

      ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

      TTL Digital I/O.

      I O

      V REF

      RA3/AN3/V

      REF

      4

      21

      21 I/O

      I I O TTL Analog Analog Analog Digital I/O.

      Analog input 2. A/D reference voltage (low) input. Analog comparator reference output.

      REF

      23 I/O

      22

      22 I/O

      I I TTL Analog Analog Digital I/O.

      Analog input 3. A/D reference voltage (high) input.

      RA4/T0CKI/C1OUT/ RCV RA4 T0CKI C1OUT RCV

      6

      23

      V REF

    PIC18F2455/2550/4455/4550

      37

      RB3/AN9/CCP2/VPO RB3 AN9 CCP2

      (1)

      VPO

      36

      12

      11 I/O

      I I/O O TTL

      Analog ST

      — Digital I/O.

      Analog input 9. Capture 2 input/Compare 2 output/PWM2 output. External USB transceiver VPO output. RB4/AN11/KBI0/CSSPP

      RB4 AN11 KBI0 CSSPP

      14

      ST — Digital I/O.

      14 I/O

      I I O TTL Analog

      TTL — Digital I/O.

      Analog input 11. Interrupt-on-change pin. SPP chip select control output. RB5/KBI1/PGM

      RB5 KBI1 PGM

      38

      15

      15 I/O

      I I/O TTL TTL ST Digital I/O.

      Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin.

      TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type

    Buffer

    Type

      Description PDIP QFN TQFP

      Analog input 8. External interrupt 2. External USB transceiver VMO output.

      PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/ FLT0/SDI/SDA

      RB0 AN12

      INT1 SCK SCL

      INT0 FLT0 SDI SDA

      33

      9

      8 I/O

      I I

      I I I/O

      TTL Analog

      ST ST ST ST Digital I/O.

      Analog input 12. External interrupt 0. Enhanced PWM Fault input (ECCP1 module). SPI data in.

      I

      2 C™ data I/O.

      RB1/AN10/INT1/SCK/ SCL RB1 AN10

      34

      10 I/O

      10

      9 I/O

      I I I/O I/O

      TTL Analog

      ST ST ST Digital I/O.

      Analog input 10. External interrupt 1. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I

      2 C mode.

      RB2/AN8/INT2/VMO RB2 AN8

      INT2

      VMO

      35

      11

      I I O TTL Analog

    PIC18F2455/2550/4455/4550

      44 I/O O

      RC5/D+/VP RC5 D+

      VP

      24

      43

      43 I I/O

      I TTL —

      TTL Digital input.

      USB differential plus line (input/output). External USB transceiver VP input. RC6/TX/CK

      RC6 TX CK

      25

      44

      I/O ST

      TTL Digital input.

      — ST Digital I/O.

      EUSART asynchronous transmit. EUSART synchronous clock (see RX/DT).

      RC7/RX/DT/SDO RC7 RX DT SDO

      26

      1

      1 I/O

      I I/O O ST ST ST

      — Digital I/O.

      EUSART asynchronous receive. EUSART synchronous data (see TX/CK). SPI data out.

      TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type

    Buffer

    Type

      Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

      ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power

      USB differential minus line (input/output). External USB transceiver VM input.

      PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI

      RC0 T1OSO T13CKI

      I I/O O ST CMOS ST

      15

      34

      32 I/O O

      I ST —

      ST Digital I/O.

      Timer1 oscillator output. Timer1/Timer3 external clock input. RC1/T1OSI/CCP2/ UOE RC1 T1OSI CCP2

      (2)

      UOE

      16

      35

      35 I/O

      — Digital I/O.

      42 I I/O

      Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. External USB transceiver OE output. RC2/CCP1/P1A

      RC2 CCP1 P1A

      17

      36

      36 I/O I/O

      O ST ST TTL Digital I/O.

      Capture 1 input/Compare 1 output/PWM1 output. Enhanced CCP1 PWM output, channel A.

      RC4/D-/VM RC4

      D-

      VM

      23

      42

      I TTL —

    PIC18F2455/2550/4455/4550

      PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). These pins have TTL input buffers when the SPP module is enabled.

      4 I/O I/O

      Streaming Parallel Port data. RD5/SPP5/P1B

      RD5 SPP5 P1B

      28

      3

      3 I/O I/O

      O ST TTL — Digital I/O.

      Streaming Parallel Port data. Enhanced CCP1 PWM output, channel B.

      RD6/SPP6/P1C RD6 SPP6 P1C

      29

      4

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